Welcome To Verification Excellence
"Learn, Excel and Advance in Functional Verification "

ABOUT

This website is a comprehensive knowledge base for learning and enhancing the skills required for becoming an excellent Verification engineer in VLSI industry. Whether you are a recent college graduate looking to learn some industry specific skills or an experienced engineer, you will find several resources that will help you to learn continuously and enhance your skills.

BOOKS

3DBookKindleMobile

Cracking Digital VLSI Verification Interview:

A Golden Reference guide that will help you prepare for a successful Digital VLSI Verification Interview.

Online Courses​

Following self paced online courses are available and are recommended to be learned in the following order.

ib
SOC Verification Using System Verlog

This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies.

verilog
Learning System Verilog Assertions and FCC

A course that will teach you everything about SVA and Functional coverage coding which forms the basis for the Assertion based and Coverage Driven Verification methodologies.

185304_7033_4
Learn to build OVM/UVM Testbenches from scratch

This course teaches the basic concepts of two (similar) methodologies - OVM and UVM - and helps you get started on coding and building actual testbenches from grounds up.

learn-to-code-what-is-programming
Cracking Programming Questions

In the present day scenario where Digital VLSI Designs are trending towards SOC designs with increased complexity, the Design Verification job is visibly becoming more and more software oriented.

TESTIMONIALS

 -Ranjan
-Ranjan
Book is a must have for new graduates who wants to enter the field of VLSI. Covers a broad range of topics from basic to advanced.A great tool to brush up all the concepts.
-Rohan
-Rohan
Great Content and Very Precious wisdom in blogs. Truly great forum to learn Verification skills.
-Sharath
-Sharath
Great place to learn. The material is very good. Practical application and taught very well.
-Keerthi
-Keerthi
Very Good Course for Kick start of verification using System Verilog and UVM.

Blogs

Verification, Validation, Testing of ASIC/SOC designs – What are the differences?

If you are involved in any ASIC/SOC design life cycle, it is highly likely that you would have heard questions ...
Read More

IP and VIPs in VLSI Design

An  Intellectual Property (IP) core in Semiconductors is a reusable unit of logic or functionality or a cell or a layout design  ...
Read More

My top answers of 2017 across VLSI, Semiconductor, Verification, Interviews and Career

Another year of writing on Quora completed (2017) with more than 300+ answers. That fell short slightly below my goal ...
Read More

View More Tutorials

Get in touch with us