Welcome To Verification Excellence
"Learn, Excel and Advance in Functional Verification "


This website is a comprehensive knowledge base for learning and enhancing the skills required for becoming an excellent Verification engineer in VLSI industry. Whether you are a recent college graduate looking to learn some industry specific skills or an experienced engineer, you will find several resources that will help you to learn continuously and enhance your skills.



Cracking Digital VLSI Verification Interview:

A Golden Reference guide that will help you prepare for a successful Digital VLSI Verification Interview. 

Online Courses​

Following self paced online courses are available and are recommended to be learned in the following order.

SOC Verification Using System Verlog

This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies.

Learning System Verilog Assertions and FCC

A course that will teach you everything about SVA and Functional coverage coding which forms the basis for the Assertion based and Coverage Driven Verification methodologies.

Learn to build OVM/UVM Testbenches from scratch

This course teaches the basic concepts of two (similar) methodologies - OVM and UVM - and helps you get started on coding and building actual testbenches from grounds up.

Cracking Programming Questions

In the present day scenario where Digital VLSI Designs are trending towards SOC designs with increased complexity, the Design Verification job is visibly becoming more and more software oriented.


Book is a must have for new graduates who wants to enter the field of VLSI. Covers a broad range of topics from basic to advanced.A great tool to brush up all the concepts.
Great Content and Very Precious wisdom in blogs. Truly great forum to learn Verification skills.
Great place to learn. The material is very good. Practical application and taught very well.
Very Good Course for Kick start of verification using System Verilog and UVM.


Implementing randc behavior using regular constraints in SystemVerilog

In SystemVerilog, variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random ...
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What is a Verification Test plan ?

What is a Verification Test plan? What are details to be included in a Test plan? Why is it important ...
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How similar is an ASIC verification job compared to a Software coding profile?

An ASIC or SOC Verification job is increasingly becoming like a Software coding and debugging profile. However what is different ...
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