Month: February 2019

Implementing randc behavior using regular constraints in SystemVerilog

In SystemVerilog, variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range.  For eg: consider  a 2 bit variable declared as     randc bit [1:0] y; Every time this variable is randomized,  the values are iterated over the possible range (in this case 0,1,2,3)  …

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How similar is an ASIC verification job compared to a Software coding profile?

An ASIC or SOC Verification job is increasingly becoming like a Software coding and debugging profile. However what is different is that you also need to be thinking like a hardware engineer while you apply some of the software engineering practices in coding and debug. Most of Verification infrastructure (test bench, stimulus generation, build, regression, …

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