This  links  contains  references and links to lot of materials that can be used  along with the online courses to enhance your learning and to keep practicing more

  1. General:     This  section gives you   reference to   Language reference manual,  useful books in SystemVerilog language, some of the important  forums and blogs that you can follow to actively learn and stay up to date on latest developments
  2. GitHub Reference:    This  links to the GitHub  repository for Verification excellence.  All  reference example for the SystemVerilog course as well as the UVM  course,  reference project etc are available here for reference or download
  3. Community discussion on Slack:  This is a  new community channel  on Slack  that helps to have live discussions – either related to course or other general topic,  thus  making best use of the  power of  a community of learning students.  If you are interested in join, mail  on