Language Reference Manuals 

  1. SystemVerilog Language Reference Manual –  1800-2012 Standard
  2. SystemVerilog Reference Guide – Very useful reference from Aldec
  3. UVM Class reference guide from  Accelera   This is 1.1d version. Search for 1.2 if you are interested
  4. UVM User guide from Accelera
  5. UVM cook book from Mentor Graphics

Books

In terms of books,  1 and 2 are the best books to learn the  SystemVerilog language and how to use the same for a Verification job. Book 3) is a good one in terms of understanding language gotchas and is a fun read and understanding your regular mistakes.  Book 4) is the best for  learning Assertions while  book 5) and  6) are option:

  1. Writing Testbenches using SystemVerilog – Janick Bergeron
  2. SystemVerilog for Verification – Chris Spear
  3. Verilog and System Verilog Gotchas – Stuart Southerland
  4. SystemVerilog Assertions Handbook: –for Formal and Dynamic Verification – By Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari
  5. Principles of Functional Verification – Andreas Meyer
  6. System Verilog Assertions and Functional Coverage – Guide to Language Methodology and Applications by Ashok B Mehta

Tutorials:

Though there are several websites, I have found following two to be good enough for all references

  1. Verification tutorials on Testbench.in
  2. Doulos tutorials on SV,UVM 

Papers from Conferences:

  1. Related to SystemVerilog usage
    1. SV coding guidelines for performance – From Mentor Verification Academy
  2. SystemVerilog Assertions
    1. SVA Assertion – Design Tricks and Binds
  3. Related to OVM/UVM Methodology
    1. A practical Subset of UVM for rapid adoption – DVCon 2015 paper    –   This is a very useful paper and  helps you understand that only a small practical subset of UVM features is all that you need to know to get started. So dont get lost in a whole lot of things
    2. OVM & UVM Test Termination Techniques  – DVCon Paper   –  Lot of details of how to end test are missing in guides and this seems has a good reference
    3. OVM & UVM Factory and Factory overrides – Sunburst design Paper  – Understand in detail about Factory concepts
    4. UVM Guildelines from Mentor Graphics – Verificaiton Academy  – Coding guidelines as suggested by Mentor Graphics
    5. UVM Messaging – Capabilities and guidelines from Sunburst – SNUG 2014 paper  – Message capability. Again this is missing in userguide
    6. Sequence on the Wall – DVCon 2013  –  Examples on how to write  reusable and advanced sequences
    7. Seven Separate Sequence Styles for Speed – DVCon 2013 –    Good illustration of different styles of sequence coding . Read this to engineer better sequence designs for stimuluss

Following are the three forums that you would want to gain access and subscribe to questions and also try answering

  1. Verification Academy Forums from Mentor Graphics
  2. Verification Guild Forums
  3. Accelera Forums

Blogs:

While there are a lot of blogs available on Verification, following three are a must follow and read on a regular basis.

  1. Verification Horizons from Mentor Graphics
  2. Verification on Web from CVC
  3. SystemVerilog Blog Spot