This contains a sample list of questions related to Digital Logic Design.  Since the job of a verification engineer is to  verify the functional correctness of Digital Logic,  this section forms a crucial part of any interview process.

This is never a complete list, but  try to focus your learning and preparation using this.

  1. What is the difference between Combinational and Sequential circuits?
  2. Simplify the following logic function f(ABC) using K-maps     f(A,B,C) =  ( A + B + C’) . (A + B’+ C’)
  3. What is the difference between “Ripple Carry Adder” and “Carry Look-ahead Generator”?
  4. What is  the concept of “Setup” and “Hold” time?
  5. How can you implement and/or/not gate using NAND/NOR?
  6. What is the difference between flip flop and latches?
  7. What is the difference between synchronous reset and asynchronous reset?
  8. What is meant by clock domain crossing?
  9. Design a state machine to detect a   stream of  “1011”  in a  serial input stream?
  10. How many flip flops are needed to implement a 32 bit register ?
  11. Explain the difference  between binary and gray encoding and the benefits of each?
  12. What is one hot encoding ?
  13. What is meant by race condition ?
  14. Design a circuit to  divide a clock  by  2 ? and  by 3 ?
  15. What is 1’s complement and 2’s complement?
  16. Which gates are called universal gates and why?