This contains a sample list of questions related to SystemVerilog that can be asked though it is never a complete list.

Learn about the language from the LRM/books and the online courses.  Also keep practicing with short projects  which is a nice way to make learning thorough

  1. What is the difference between  bit and logic  data types?
  2. What is the difference between  logic[7:0] and byte  data type?
  3. What is the difference between  queues, dynamic arrays and associative arrays?
  4. What is the difference between a class and object?
  5. What is  inheritance  and multiple inheritance? Does SystemVerilog support multiple inheritance?
  6. What is a virtual function?
  7. What is the difference  between  a static  member of a class and non-static member of class?
  8. What is the difference between  overriding a method   vs   overloading a method?  Does SystemVerilog support both?
  9. What is meant by forward declaration of a class and when is it used?
  10. What is a “ref” and  “const  ref” argument  in SystemVerilog functions?
  11. Can  a static function  have an argument with “ref” keyword?
  12. What is the difference between pass by reference and pass by value ?
  13. What is the difference between  “==”  and  “===”  logical equality operators?
  14. Which of the logical equality operator  “==”  or “===” i s used by   case statements to detect condition match?
  15. What is the difference between   fork..join_none and  fork..join_any ?
  16. What is the  use of modports inside  clocking blocks?
  17. What is the difference between  pre and post increment operators –   ++a   vs  a++ ?
  18. What is a  bind  construct used for in SystemVerilog?
  19. What is the difference between  immediate and concurrent assertions?
  20. What is the difference  between overlapping and non-overlapping implication operators?