The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs.
This course teaches
- Basic concepts of two (similar) methodologies – OVM and UVM –
- Coding and building actual testbenches based on UVM from grounds up.
- Plenty of examples along with assignments (all examples uses UVM)
- Quizzes and Discussion forums
- Hands on assignment to build a complete UVM Verification environent for a most popular SOC Bus protocol – APB Bus
What are the requirements?
- Basic understanding of Functional Verification concepts
- Basic understanding of SystemVerilog and object oriented concepts
- Motivation to learn and discuss questions in the Forums
What am I going to get from this course?
- Over 36 lectures and 5.5 hours of content!
- Understand concepts behind OVM and UVM Verification methodologies
- Start coding and build testbenches using UVM or OVM Verification methodology
What is the target audience?
- Verification engineers who have basic understanding of SystemVerilog but new to OVM/UVM methodology
- Students passing out of VLSI/DigitalDesign/Microelectronics looking for a job in front end of VLSI design
- Any VLSI front end design/verification engineer who wants to increase their job opportunities and skills
Introduction and Welcome to Course (3:33)
Course Resources and Instructions (2:53)
Need for Standard Verification Methodologies (13:58)
Layered Testbench Architecture (14:56)
Download Course Resources And Assignment Instructions (18:39)
Introduction to OVM/UVM Concepts (7:12)
Transaction Level Modelling Basics (15:01)
TLM Interfaces – Ports, Exports and FIFOs (15:01)
TLM Interfaces – Analysis Ports and FIFOs (3:41)
Assignment 1 – Producer Consumer Example with TLM1 – Coding and Simulating (7:32)
Testbench Component And Hierarchy (14:59)
Building Driver and Sequencer Components (13:53)
Sequencer to Driver Connection (11:34)
Building a Monitor Component (8:00)
Building an Agent Component (9:58)
Environment and Test Class Components (9:53)
Building and Connecting Testbench Components (15:01)
Understanding Simulation Phases (13:23)
Sequence Based Stimulus Generation