SOC Verification Using System Verilog

A comprehensive course that teaches System on Chip design Verification Concepts and Coding in SystemVerilog Language

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Course Description

This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language – which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.

 

Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course

What are the requirements?

  • Basic digital design or awareness to chip design flows
  • Passion for learning

What you are going to get from this course?

  • Over 35 lectures and  nearly  5 hours of content!
  • Learn the important concepts in SOC/ASIC/VLSI design verification flow
  • Learn the System Verilog language for Functional Verification usage
  • Be ready and qualified for a Verification job in semiconductor industry
  • Udemy Certification on successful course completion
  • Be able to code, simulate and verify SystemVerilog Testbenches

 

What is the target audience?

  • Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry
  • Digital Design and Verification Professionals who are passionate about continuous learning

 

Curriculum

Welcome to Course – Introduction
  • Itroduction and Overview (4:15)
  • Introducing Yourself
  • Introduction to SOC and VLSI Design Flows (5:00)
  • Course Resources (18:39)
  • Quiz 1 : Test your Awareness
Verification Basics and Concepts
  • Verification – What , Why and How ? (7:23)
  • Verification – Planning, Approaches, Metrics (9:17)
  • Verification Methodologies – Simulation , Formal and Assertions (13:57)
  • Directed Vs Constrained Random Verification and Coverage (12:59)
  • Other Trends – HW+SW Verification and Emulation (8:14)
  • Quiz 2: Test your Verification Concepts
  • Exercise 1: Case Study with a Design to be verified (9:08)
Introduction to System Verilog Language
  • History and Overview of System Verilog (6:20)
  • Language Constructs: DataTypes And Operators (10:41)
  • Language Constructs: Loops and Flow control (6:59)
  • System Verilog Tasks and Functions (5:06)
  • Quiz 3 : Test your SystemVerilog Basics
  • SV Arrays and Queues (13:53)
  • Exercise 2: Coding of a design to be verified (18:39)

 

Basic System Verilog Test bench Constructs
  • Interfaces (8:40)
  • Clocking Blocks (5:26)
  • Program Blocks (6:16)
  • Direct Programming Inteface (DPI) (18:39)
  • Quiz 4: Test your SV TB Basics
  • Exercise 3 : Coding Interfaces and Clocking Blocks (18:39)
System Verilog – OOP Concepts and Randomization
  • Basic OOP Concepts (7:34)
  • System Verilog Classes Explained (15:01)
  • Virtual Interfaces (7:35)
  • Random Constraints and Usages – Part 1 (9:42)
  • Random Constraints : Part 2 (8:00)
  • Quiz 5: Test your basics on System Verilog Classes
  • Exercise 4: Building Class based Testbench components (18:39)
Threads and Inter Process Communication
  • Process and Threads in System Verilog (6:22)
  • System Verilog Mailboxes (6:50)
  • Synchronization – Events and Semaphore (8:45)
  • Exercise 5: Connecting all TB components using Mailboxes (18:39)
  • Exercise 6: Build Top TB and compile etc (18:39)
  • Quiz 6: Test your Advanced System Verilog Knowledge
Introduction to Verification Methodologies
  • Standard Verification Methodologies – Need and Evolution (8:17)
  • Introduction to concepts – OVM and UVM (6:15)
Course Wrap up and Summary
  • Summary, Leanings and Future Topics (4:50)
  • Course Improvement Survey

 

FAQs

When does the course start and finish?
The course starts now and never ends! It is a completely self-paced online course – you decide when you start and when you finish.
How long do I have access to the course?
How does lifetime access sound? After purchase, you have unlimited access to this course for as long as you like – across any and all devices you own.
What if I am unhappy with the course?
We would never want you to be unhappy! If you are unsatisfied with your purchase, contact us in the first 30 days and we will give you a full refund.