One of the big job opportunities in VLSI Design spectrum is front end verification engineer. The demand for verification engineers has been increasingly over last decade and is also getting more and more importance.
Note: If you are new to VLSI Design life cycle, you might want to read VLSI – Front end vs Back end – opportunities first
Front end Verification Engineer Career
There is a lot of confusion among entry level engineers on what opportunities exists for a VLSI Front end verification engineer career? Many think it is a testing job and consider it as second to a design job. Having worked in this field for close to two decades, I want to share my thoughts on how one can build a career as a Verification Engineer and what all opportunities exist.
If you want a quick snippet of what I am going to share, you can quickly read following slides, which is a talk that I did a year back to a group of young engineers.
One of the common question that every one has is what will I be doing in 5 years if I start working as a verification engineer. Will I be able to switch to a design engineering job? Will the job be interesting? Will I be only testing and debugging? What all are the challenges?
Verification Engineer Career – Facts
Based on my experience, I can tell for sure that there are lot of opportunities and a strong career path for verification engineers. Over the last several years, complexity of designs have increased and continues to increase. Verifying a design is always crucial as any functional defect in the manufactured chip is going to cost huge money in terms of a new tape out as well as there is the risk of losing a design win opportunity in market. In the life cycle of a design, there are always bugs to be found in lesser time in every project.
A good verification engineer need to have both hardware and software engineering skills. Along with strong foundation in Digital logic design , Computer architecture , Communication technologies and other domain knowledge, he should be a good programmer too. Most of current Verification infrastructure uses advanced software engineering concepts like Object oriented programming, factory patterns, continuous integration mechanisms as well as Hardware description languages like SystemVerilog and VHDL
You might want to read – What makes a great Verification Engineer Career? for more details.
Opportunities – Verification Engineer
Functional Verification still is is the major part of any Verification project cycle with Simulation based methodologies used primarily.
Formal Verification methodologies are selectively applied for specific aspects of a design. Functional Verification typically starts along with design development and some of the advanced constrained random test benches demands a lot of software programming skills along with hardware skills.
Performance Verification focuses on verification of performance aspects of the design
Power aware verification has gained lot of importance in last several years and the focus is to verify the low power design techniques implemented.
Clocking and CDC Verification has gained importance with multiple asynchronous clocks in the modern designs and has its own methodologies.
DFT (Design for Testing ) and DFM (Design for Manufacturing) involves specific design techniques to facilitate silicon testing and validation. Verifying these is orthogonal to functional testing and focuses on verifying the specific debug support techniques.
FPGA Prototyping and emulation is also currently gaining increased importance with larger and complex SOC designs. These helps in accelerating the functional verification and also stress testing with long stimulus patterns.
Hardware+Software Co-Verification is another approach used to have software development and testing progressing along with Hardware development and helps in more robust validation and identifying both software and hardware bugs before tape out.
For more learning checkout VLSI Online courses related to Verification
Also if you have a question, check out my Quora profile or ask a question