Here are some good books that I have found useful in my experience over last several years

  1. Writing Testbenches using SystemVerilog – Janick Bergeron
  2. SystemVerilog for Verification – Chris Spear
  3. Principles of Functional Verification – Andreas Meyer
  4. Verilog and System Verilog Gotchas – Stuart Southerland
  5. SystemVerilog Assertions Handbook: –for Formal and Dynamic Verification – By Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari
  6. System Verilog Assertions and Functional Coverage – Guide to Language Methodology and Applications by Ashok B Mehta

There are also several other tutorial and online courses/video lectures available and tools like  EDA Playground to keep practicing your coding skills as well.

Good luck in learning


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What are the best books/resources for learning SystemVerilog ?