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SystemVerilog is a superset and an extension to Verilog language.  To understand how it evolved, it will be good to understand the history briefly on how it evolved
Verilog_SV
Verilog language began in 1983 as a proprietary language for hardware modelling at Gateway Design Automation Inc.  Gateway Design Automation was later acquired by Cadence in 1990 and continued enhancements. It later became  IEEE standard 1364  in  1995 and started becoming more widely used.  There were two major enhancements to Verilog later  in 2001 and 2005.
In the same time frame, design complexities were increasing and the enhancements in Verilog standard was primarily for  RTL constructs.
Verification methodologies also evolved in same time frame to deal with efficient verification of complex designs.  Constrained random verification with Coverage and Assertion based verification were becoming more useful.
Since Verilog language did not have support for same,  several other  Verification oriented  languages  like Vera and Specman were becoming widely used in industry as those supported  most of the constructs needed for  verification in terms of modelling, stimulus , assertions etc. But these languages were  limited to specific vendors and not any IEEE standard.
SystemVerilog was originally intended as an extension to Verilog 2005 and became IEEE standard 1800.   It was published as a seperated documented and consists of hundreds of enhancements and extensions to verilog.  In 2009 it  officially became a super set of Verilog  and  was again updated in 2012   as   IEEE 1800-2012 standard.
There were  5 major  areas where enhancements were added in SystemVerilog
1) SVD – System Verilog for Design.   This includes several enhancements to design constructs .
2) SVTB – SystemVerilog for Testbenches: This was the biggest set of enhancement in SystemVerilog for support all the Testbench modelling and needs for newer verification methodologies.
This includes  at a high level  – Object Oriented Programming support with Classes,  a constraint solver with several capabilities for creating constrained random stimulus, concurrent processes, semaphores, mailboxes and many more.
3) SVA – System Verilog Assertions : This includes several Features for temporal and concurrent assertions  like  properties and sequences.
4) SVDPI – SV Direct Programming Interface:  This includes  features for better C/C++ integration
5) SVAPI – SV Application Programming Interface: This includes features for better  intergration of APIs for  Coverage and assertions
For more details refer to the IEEE 1800.2012 spec – 1800-2012 Standard

 

What are the differences between verilog and systemverilog?