My answer to What is expected from a very good ASIC verification engineer?
Answer by Ramdas Mozhikunnath:
It is not just learning methodology or knowing about a protocol that makes a good verification engineer. Those are just two skills that will help you in short term for your job, but you need to have a bigger picture for long term success.
Based on my more than decade of experience as a Verification engineer – what I have learned and what I have observed as traits of several successful and exceptional verification engineers – I will try to list down some of the points
- Solid knowledge about design under test (DUT) – Whether you are working on a protocol IP verification or one or more portions of a complex designs like a CPU/networking chip/wireless chip – you need to understand all aspects of the design specification. This knowledge is what will help you in several other key aspects of verification like:
- Defining a proper verification plan and identifying all features and corner cases for testing
- Identifying right methodology for different features – Some might be best verified with simulation while some others might be ideal for formal verification or emulation etc.
- Architecting and implementing efficient testbenches – defining stimulus, drivers, checkers, coverage etc
- Debugging simulation failures, identifying bugs, proposing fixes etc.
- Defining coverage and other metrics for Verification completeness
- Developing debug skills – Be persistent Debug is going to be your part of every day job. Whether you are developing a test bench, simulating a test, analyzing a coverage, looking at regression failures etc, you will need to be persistent in debugging and getting down to root cause every time. Your solid knowledge of design is going to help a long way in this and once you master this, I feel all other skills will improve.
- Following is a slide from Mentor’s blog () which shows that a verification engineer spends most of time in debug
- Programming skills, knowledge of Verification methodologies
- Good understanding of programming concepts and a verification language like SystemVerilog and a methodology like OVM/UVM is expected of a Verification engineer – However these are skills that you keep learning and with a right attitude can be mastered with practice and practice.
- Other miscellaneous traits that will help you in being successful are
- Working closely with design engineers, develop curiosity, ask questions, suggest solutions
- Working towards continuous improvement and high quality – always try to improve on your skills with no sacrifice on quality – high standards of coding, being paranoid of every single failure etc
- Ability to effectively communicate and report issues to peers and team with well understood details
- Prioritization of tasks and risks – as not everything can be done always in a given time.