Answer by Ramdas Mozhikunnath:

This classification is based on the different steps involved in a typical VLSI design flow.  Following diagram shows a typical design flow for an ASIC or  SOC or any VLSI chip design…
As  the flow shows, any design starts with  specification followed by translating the specification to a high level design and then into a low level design.  The high level design involves  designing the functional blocks and the communication protocol between them. The low level design involves  translating into actual modules that contain FSMs, combinational and sequential circuits etc.
Following by this, the design is modelled using a HDL (Hardware description language like Verilog/VHDL)  which is the RTL coding stage.
In Functional Verification stage, this  HDL model is then verified for Functional correctness using  different Verification methodologies and refined until the HDL model is proved to be meeting the specifications
All tasks till this stage is  normally called as the Front end of VLSI design and are executed by Front end Engineers
The next step is to synthesize  the HDL model to a target technology to obtain a gate level design.  This step is done  normally in collaboration by a  front end design engineer and a back end design engineer who  takes this  gate level netlist  for further steps till fabrication
All steps after logic synthesis  are  performed by  back end engineers and forms the back end steps to take this netlist to fabrication of the chip.
This involves  Placement and Routing where  all the gates and flip-flops are placed,  Clock tree synthesis and reset  routing etc. After this each block is routed, output of the P&R tool is a GDS file, which is used by a foundry for fabricating the ASIC.  Gate level simulations and  Static Timing Analysis are also done to make sure that the  gate level design meets the timing requirements for correct design operations. Further  this   GDS file  is sent to the foundry for manufacturing.
In terms of future,  both  front end and back end design steps are equally important and involves   equal but different kinds of challenges for successful chip designs.
So I cant really distinguish between both and have seen equal opportunities for both in most of my  experience in this industry.
Hope this helps and feel free to let me know any comments/questions.

What is the difference between a VLSI frontend engineer and Backend engineer and who has more bright future?

What is the difference between a VLSI frontend engineer and Backend engineer and who has more bright future?
  • viswa nethra

    I am a VLSI fresher and please tell me what I have to learn in order to enter into VLSI industry as front-end design engineer(Both design and verification).
    In design is VHDL and Verilog languages are enough or still I have to learn.
    In verification is SOC Verification (Functional Verification) is enough or any other like UVM or UVM+ is necessary.