My answer to Why do we use C language for SoC tests? Why not System Verilog?
Answer by Ramdas Mozhikunnath:
An SOC has one or more processors (cpus or microcontollers or dsp etc) at the heart of it . All other logic constituting the system are around it. (peripherals, memory/controllers, network etc)
A processor executes a software program (and multiple layers in real world) in terms of instructions. It will always fetch instructions from the memory and execute them which will trigger the various logic around it in the SOC
This is why most of SOC level tests are in a high level language like C. It need not be strictly C, but could be in other languages which all finally translates to the correct assembly code and an object file that can be loaded in to the memory. ( I have seen Python/Perl also popular to generate SOC level test cases).
You cannot use SystemVerilog to create a program for the processor to execute. However if you are replacing the processor and some subsystems of SOC with behavioral models – kind of a sub system – then for that verification you can use SystemVerilog.
On a related note, you might want to watch theinitiative from Accelera with an intend to standardize stimulus across various platforms