FunctionalVerification

Posts related to Functional Verification

Implementing randc behavior using regular constraints in SystemVerilog

Blogs, SystemVerilog and UVM / By

In SystemVerilog, variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range.  For eg: consider  a 2 bit variable declared as     randc bit [1:0] y; Every time this variable is randomized,  the values are iterated over the possible range (in this case 0,1,2,3)  …

Implementing randc behavior using regular constraints in SystemVerilog Read More »

How similar is an ASIC verification job compared to a Software coding profile?

FunctionalVerification, VLSI Career / By

An ASIC or SOC Verification job is increasingly becoming like a Software coding and debugging profile. However what is different is that you also need to be thinking like a hardware engineer while you apply some of the software engineering practices in coding and debug. Most of Verification infrastructure (test bench, stimulus generation, build, regression, …

How similar is an ASIC verification job compared to a Software coding profile? Read More »

Verification Engineer Career Path

Verification Engineer Career- Opportunities and Path

Blogs, FunctionalVerification, VLSI Career, VLSI Design / By

Introduction One of the big job opportunities in VLSI Design spectrum is  front end verification engineer. The demand for verification engineers has been increasingly over last decade and is also getting more and more importance. Note: If you are new to VLSI Design life cycle, you might want to read  VLSI – Front end vs …

Verification Engineer Career- Opportunities and Path Read More »

What is a p_sequencer and an m_sequencer in UVM?

SystemVerilog and UVM / By

In SystemVerilog based OVM/UVM methodologies,  UVM sequences are objects with limited life time unlike a component which has a lifetime through out simulation. UVM Testbench – Sequences vs  Components Refer following standard UVM test bench diagram for a general concept.  All components like  test, env, scoreboard, agent, monitor, sequencer and driver  are derived from   uvm_component  …

What is a p_sequencer and an m_sequencer in UVM? Read More »

Verification Validation Testing

Verification, Validation, Testing of ASIC and SOC designs – What are the differences?

Blogs, FunctionalVerification, Latest Posts / By

Do you know differences between Verification, Validation and Testing of ASIC / SOC designs in the VLSI/chip design life cycles? If you are involved in any ASIC/SOC design life cycle, it is highly likely that you would have heard questions like – Have you verified a feature?  Is all feature testing completed?  How will you …

Verification, Validation, Testing of ASIC and SOC designs – What are the differences? Read More »

My top answers of 2017 across VLSI, Semiconductor, Verification, Interviews and Career

Blogs, FunctionalVerification, Latest Posts, VLSI Career / By

Another year of writing on Quora completed (2017) with more than 300+ answers. That fell short slightly below my goal of averaging an answer per day. Nevertheless it has been another wonderful experience. I am happy to have helped those in need through these answers in the last year related to VLSI, Semiconductor and related …

My top answers of 2017 across VLSI, Semiconductor, Verification, Interviews and Career Read More »

Cracking Digital VLSI Verification Interviews: Interview Success – A unique book

Blogs, FunctionalVerification, Latest Posts, VLSI Career / By

A large number of jobs in semiconductor industry fall in the category of Digital VLSI Design and Verification. With digital designs becoming more and more complex, demand of Digital VLSI Verification Engineers is on the rise. Increase in design complexity has not only led to an increase in the number of VLSI Verification jobs but …

Cracking Digital VLSI Verification Interviews: Interview Success – A unique book Read More »

Verification Interview Questsions

What are your best ASIC Verification Interview Questions?

Blogs, FunctionalVerification, Latest Posts, SystemVerilog and UVM / By

This question arises in every one’s mind while preparing for an ASIC Verification Interview. A lot of times in addition to understanding the technical concepts, you also needs to focus your preparation aligning with expectations from the interviewer and practice some of the commonly asked questions. This helps you to gain confidence and answer any related …

What are your best ASIC Verification Interview Questions? Read More »

error

Enjoy this blog? Please spread the word :)