Functional Verification of VLSI designs
What is a Verification Test plan? What are details to be included in a Test plan? Why is it important in functional Verification? What are some sample test plan templates? How is a Verification Test plan used and helpful? Design Specification A design specification (also known Architecture/ Micro architecture Specification) is a document that is …
Introduction One of the big job opportunities in VLSI Design spectrum is front end verification engineer. The demand for verification engineers has been increasingly over last decade and is also getting more and more importance. Note: If you are new to VLSI Design life cycle, you might want to read VLSI – Front end vs …
Verification Engineer Career- Opportunities and Path Read More »
Do you know differences between Verification, Validation and Testing of ASIC / SOC designs in the VLSI/chip design life cycles? If you are involved in any ASIC/SOC design life cycle, it is highly likely that you would have heard questions like – Have you verified a feature? Is all feature testing completed? How will you …
Verification, Validation, Testing of ASIC and SOC designs – What are the differences? Read More »
An Intellectual Property (IP) core in Semiconductors is a reusable unit of logic or functionality or a cell or a layout design that is normally developed with the idea of licencing to multiple vendor for using as building blocks in different chip designs. In today’s era of IC designs more and more system functionality are getting integrated …
Another year of writing on Quora completed (2017) with more than 300+ answers. That fell short slightly below my goal of averaging an answer per day. Nevertheless it has been another wonderful experience. I am happy to have helped those in need through these answers in the last year related to VLSI, Semiconductor and related …
My top answers of 2017 across VLSI, Semiconductor, Verification, Interviews and Career Read More »
A large number of jobs in semiconductor industry fall in the category of Digital VLSI Design and Verification. With digital designs becoming more and more complex, demand of Digital VLSI Verification Engineers is on the rise. Increase in design complexity has not only led to an increase in the number of VLSI Verification jobs but …
Cracking Digital VLSI Verification Interviews: Interview Success – A unique book Read More »
This question arises in every one’s mind while preparing for an ASIC Verification Interview. A lot of times in addition to understanding the technical concepts, you also needs to focus your preparation aligning with expectations from the interviewer and practice some of the commonly asked questions. This helps you to gain confidence and answer any related …
What are your best ASIC Verification Interview Questions? Read More »
UVM (Universal Verification Methodology) is a SystemVerilog language based Verification methodology which is getting more and more popularity and adoption in the VLSI Verification industry. The methodology is currently in the IEEE working group 1800.2 and is expected to be an IEEE standard shortly. What are some of UVM Interview questions that can test your …
Test your UVM skills for a VLSI front end Verification job Read More »
VLSI Question and answers Another new year has arrived and it is time to commit towards New Year Resolutions and to introspect and evaluate learning from last year’s resolutions. Last year around same time, I was in the middle of writing my book and pushing towards completion. Some where in between I came across this …
Is it knowledge about a protocol or an IP ? Or learning a new methodology or a new language? Finding corner case bugs? Thinking out of box ? – How can you become a great Verification Engineer ? Whether you are a young engineer entering VLSI Verification industry or aspiring to build a great career …
