SystemVerilog

SystemVerilog language for Verification

Implementing randc behavior using regular constraints in SystemVerilog

Blogs, SystemVerilog and UVM / By

In SystemVerilog, variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range.  For eg: consider  a 2 bit variable declared as     randc bit [1:0] y; Every time this variable is randomized,  the values are iterated over the possible range (in this case 0,1,2,3)  …

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What is a p_sequencer and an m_sequencer in UVM?

SystemVerilog and UVM / By

In SystemVerilog based OVM/UVM methodologies,  UVM sequences are objects with limited life time unlike a component which has a lifetime through out simulation. UVM Testbench – Sequences vs  Components Refer following standard UVM test bench diagram for a general concept.  All components like  test, env, scoreboard, agent, monitor, sequencer and driver  are derived from   uvm_component  …

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My top answers of 2017 across VLSI, Semiconductor, Verification, Interviews and Career

Blogs, FunctionalVerification, Latest Posts, VLSI Career / By

Another year of writing on Quora completed (2017) with more than 300+ answers. That fell short slightly below my goal of averaging an answer per day. Nevertheless it has been another wonderful experience. I am happy to have helped those in need through these answers in the last year related to VLSI, Semiconductor and related …

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Cracking Digital VLSI Verification Interviews: Interview Success – A unique book

Blogs, FunctionalVerification, Latest Posts, VLSI Career / By

A large number of jobs in semiconductor industry fall in the category of Digital VLSI Design and Verification. With digital designs becoming more and more complex, demand of Digital VLSI Verification Engineers is on the rise. Increase in design complexity has not only led to an increase in the number of VLSI Verification jobs but …

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Test your UVM skills for a VLSI front end Verification job

Blogs, FunctionalVerification, SystemVerilog and UVM / By

UVM (Universal Verification Methodology) is a SystemVerilog language based Verification methodology which is getting more and more popularity and adoption in the VLSI Verification industry. The methodology is currently in the IEEE working group 1800.2 and is expected to be an IEEE standard shortly.  What are some of UVM Interview questions that can test your …

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