LEARN TO BUILD SYSTEMVERILOG BASED OVM AND UVM TESTBENCHES
The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs.
This course teaches
- Basic concepts of two (similar) methodologies – OVM and UVM –
- Coding and building actual testbenches based on UVM from grounds up.
- Plenty of examples along with assignments (all examples uses UVM)
- Quizzes and Discussion forums
- Hands on assignment to build a complete UVM Verification environent for a most popular SOC Bus protocol – APB Bus
What are the requirements?
- Basic understanding of Functional Verification concepts
- Basic understanding of SystemVerilog and object oriented concepts
- Motivation to learn and discuss questions in the Forums
What you are going to get from this course?
- Over 36 lectures and 5.5 hours of content!
- Understand concepts behind OVM and UVM Verification methodologies
- Start coding and build testbenches using UVM or OVM Verification methodology
What is the target audience?
- Verification engineers who have basic understanding of SystemVerilog but new to OVM/UVM methodology
- Students passing out of VLSI/DigitalDesign/Microelectronics looking for a job in front end of VLSI design
- Any VLSI front end design/verification engineer who wants to increase their job opportunities and skills