Welcome to Online courses that will teach you everything about basics of Functional Verification to advanced topics like SystemVerilog languages and Verification methodologies like OVM and UVM
All of these courses are self-paced and consists of video lectures along with course handouts. There are assignments/projects that are part of the course and the students are adviced to actively complete those to make best use of the course.
There is also a discussion forum associated with each lecture where students are encouraged to raise any question or even help other students
And always reach out on the contact form to share any feedback or new learning needs that you might have.
Following are the courses currently available:
A comprehensive course that teaches System on Chip Design Verification concepts and coding in SystemVerilog Language. Also consists of quizzes and assignments as part of course completion
The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs. Learn the fundamental concepts behind these methodologies and learn how to build testbenches in this methodology from scratch.
Two of the most necessary skills used in todays constrained random verification environments are developing SystemVerilog Assertion checks and Functional Coverage coding. Learn indepth about these from this course.
More courses are in works and stay tuned on this page to see when they will be available.
Good luck in learning !