General Resources


In terms of books, 1 and 2 are the best books to learn the SystemVerilog language and how to use the same for a Verification job. Book 3) is a good one in terms of understanding language gotchas and is a fun read and understanding your regular mistakes. Book 4) is the best for learning Assertions while book 5) and 6) are option:

  1. Writing Testbenches using SystemVerilog – Janick Bergeron
  2. SystemVerilog for Verification – Chris Spear
  3. Verilog and System Verilog Gotchas – Stuart Southerland
  4. SystemVerilog Assertions Handbook: –for Formal and Dynamic Verification – By Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari
  5. Principles of Functional Verification – Andreas Meyer
  6. System Verilog Assertions and Functional Coverage – Guide to Language Methodology and Applications by Ashok B Mehta


Though there are several websites, I have found following two to be good enough for all references
  1. Verification tutorials on
  2. Doulos tutorials on SV,UVM


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