Learn SystemVerilog Assertions and Coverage Coding in-depth

Become skilled in two key aspects of SystemVerilog used to ensure quality and completeness in all Verification jobs.

Course Description

A course that will help you learn everything about System Verilog Assertions (SVA) and Functional coverage coding which forms the basis for the Assertion based and Coverage Driven Verification methodologies. These are the two key methodologies used most widely in all current SOC/chip designs to ensure quality and completeness.

The course covers everything from concepts to coding along with several examples to illustrate as well as quizzes and lab exercises to make your learning thorough.

The course contents include several examples and illustrations from LRM and other popular books on SystemVerilog.

What are the requirements?

  • Basic concepts in Verification
  • A desire to learn important skills essential for a Functional Verification job

What am I going to get from this course?

  • Over 27 lectures and 5 hours of content!
  • Learn the concepts of Assertions and Functional Coverage and how to use SystemVerilog language for same
  • Gain hands on experience through examples and assignments
  • Add these key skills to your profile that are a must for getting any Verification job in current industry

What is the target audience?

  • Students of VLSI/Digital/Embedded design looking for a job in Front end VLSI design
  • Professional Logic Design and Verification Engineers who wants to increase their skills

Course Curriculum

Welcome and Overview
  • Introduction and Overview (2:21)
  • Quiz1 – Test your basics
System Verilog Assertions – Basics and Sequences
  • Introduction to Assertions (11:00)
  • SVA Basics – Immediate and Concurrent Assertions (14:56)
  • SVA Basics – Sequences and Properties (14:48)
  • Sequence Operators – Repeat operators (10:11)
  • Sequence Operators – AND , OR (11:49)
  • Sequence Operators – First_match, throughout and within (10:45)
  • Sequence Operators – if..else, ended (9:04)
  • Quiz 2 – Test your knowledge on operators
  • Sequences – Usage of Local Variables and Subroutines (11:19)
  • Sequences – Sample Value Functions (13:06)
  • Quiz 3 – Test your SVA knowledge
  • Sequences – System Tasks and Functions (7:42)
  • Exercises for Sequences (7:39)
System Verilog Assertions – Properties and Clocking
  • SVA Properties – Basics and Types (11:27)
  • SVA – Recursive Properties (10:56)
  • Clock Resolution and Multiple clk properties (12:58)
  • SVA – Binding and usage of expect statement (10:47)
  • SV Assertions – Tips and Best Practices (8:26)
  • Exercises for Assertions and Properties (8:55)
  • Quiz 4 – Test your Assertions knowledge
System Verilog – Functional Coverage Coding
  • Introduction to Coverage (13:40)
  • SV Covergroups and Coverpoints – Basics (15:01)
  • Coverage Bins – Auto, wildcard, illegal and ignore bins (15:01)
  • SV Cross Coverage (15:01)
  • SV Coverage options and usage (8:10)
  • Coverage pre-defined methods and performance implications and Cover property (13:44)
  • Quiz 5 – Testing Functional Coverage
  • Exercises for Functional Coverage (5:40)
Summary and Wrapup
  • Quiz 6 – Test your skills
  • Course Summary and Thank you (12:08)

 FAQs

When does the course start and finish?
The course starts now and never ends! It is a completely self-paced online course – you decide when you start and when you finish.
How long do I have access to the course?
How does lifetime access sound? After purchase, you have unlimited access to this course for as long as you like – across any and all devices you own.
What if I am unhappy with the course?
We would never want you to be unhappy! If you are unsatisfied with your purchase, contact us in the first 30 days and we will give you a full refund.