Here are some sample questions that will help you

1. What are some of the benefits of UVM methodology?
2. What are some of the drawbacks of UVM methodology?
3. Explain the concept of Transaction Level Modelling?
4. What is the difference between an  uvm_object and  uvm_component  class?
5. What are TLM ports and TLM Fifos?
6. What is an analysis port and analysis fifo and  where are they used?
7. Explain the  protocol handshake between  a sequencer and driver ?
8. What is the difference  between a  sequence and sequence item?
9. Is it possible to collect responses from DUT back to a sequence and if so how?
10. What is the difference between SEQ_ARB_RANDOM and SEQ_ARB_STRICT_RANDOM arbitration mechanism on sequencer?
11. What is the difference between grab() and lock() on sequencer?
12. What is the difference between a pipelined  and non-pipelined driver?
13. What is the difference between early randomization and late randomization of sequences?
14. Write a  sample  sequence code that  generates a stream of ethernet packets?
15. How can you specify weightage for a sequence when started on a sequencer?
16. What is  the difference between a monitor and a scoreboard in UVM methodology?
17. What is meant by  factory and what is its importance?
18. What is the difference between creating an object using  new()  and create()?
19. What are the difference  phases in UVM  and what is the order of their execution?
20. What are objections and how are they useful?
21. How can you implement a simulation timeout  mechanism using UVM methodology?
22. What is meant by factory override  and what are different types of overriding possible with UVM factory?
23. What is a virtual sequence and  where do we use a virtual sequence?  What are its benefits?
24. What is  uvm_config_db  and what is it used for?
25. Why should any  uvm component be registered with factory?