SOC Verification Using System Verilog
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Course Description
This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language – which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.
Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course
What are the requirements?
- Basic digital design or awareness to chip design flows
- Passion for learning
What you are going to get from this course?
- Over 35 lectures and nearly 5 hours of content!
- Learn the important concepts in SOC/ASIC/VLSI design verification flow
- Learn the System Verilog language for Functional Verification usage
- Be ready and qualified for a Verification job in semiconductor industry
- Udemy Certification on successful course completion
- Be able to code, simulate and verify SystemVerilog Testbenches
What is the target audience?
- Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry
- Digital Design and Verification Professionals who are passionate about continuous learning