An ASIC or SOC Verification job is increasingly becoming like a Software coding and debugging profile.
However what is different is that you also need to be thinking like a hardware engineer while you apply some of the software engineering practices in coding and debug.
Most of Verification infrastructure (test bench, stimulus generation, build, regression, triage) all needs coding.
Most of current complex designs are functionally verified using simulation and the test bench infrastructure is coded usingobject oriented programming concepts. SystemVerilog language and the UVM base class (and methodology) all heavily uses the same.
Most companies have emphasis on coding guidelines, reviews and best practices just like software development. You will also need to be familiar with version control systems (CVS, Perforce, Git etc) to good extend
Most of designs and the verification infrastructure are complex and developed by small to big teams – and practices likecontinuous integration for builds and release are adopted by Verification engineers just like Software engineers(e.g Jenkins)
There is a lot of scope ofautomation of routine jobs of verification engineer – and scripting languages like Python/Perl are heavily used. (regressions, triage, machine pool management etc)
Verification engineers also spend a considerable time in debug of their own code as well as the RTL (model of hardware design). This is where you will need to understand code that looks like software (Verification code) as well as think like a hardware engineer (looking at RTL and simulation wave forms)
With all that said, it is fun , lot of challenges and learning !
