Implementing randc behavior using regular constraints in SystemVerilog
In SystemVerilog, variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range. For eg: consider a 2 bit variable declared as randc bit [1:0] y; Every time this variable is randomized, the values are iterated over the possible range (in this case 0,1,2,3) …
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