Month: August 2018

Verification Engineer Career Path

Verification Engineer Career- Opportunities and Path

Introduction One of the big job opportunities in VLSI Design spectrum is  front end verification engineer. The demand for verification engineers has been increasingly over last decade and is also getting more and more importance. Note: If you are new to VLSI Design life cycle, you might want to read  VLSI – Front end vs …

Verification Engineer Career- Opportunities and PathRead More »

What is a p_sequencer and an m_sequencer in UVM?

In SystemVerilog based OVM/UVM methodologies,  UVM sequences are objects with limited life time unlike a component which has a lifetime through out simulation. UVM Testbench – Sequences vs  Components Refer following standard UVM test bench diagram for a general concept.  All components like  test, env, scoreboard, agent, monitor, sequencer and driver  are derived from   uvm_component  …

What is a p_sequencer and an m_sequencer in UVM?Read More »

Enjoy this blog? Please spread the word :)