What is a p_sequencer and an m_sequencer in UVM?
In SystemVerilog based OVM/UVM methodologies, UVM sequences are objects with limited life time unlike a component which has a lifetime through out simulation. UVM Testbench – Sequences vs Components Refer following standard UVM test bench diagram for a general concept. All components like test, env, scoreboard, agent, monitor, sequencer and driver are derived from uvm_component …
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