Posts related to Functional Verification
UVM (Universal Verification Methodology) is a SystemVerilog language based Verification methodology which is getting more and more popularity and adoption in the VLSI Verification industry. The methodology is currently in the IEEE working group 1800.2 and is expected to be an IEEE standard shortly. What are some of UVM Interview questions that can test your …
Test your UVM skills for a VLSI front end Verification job Read More »
Is it knowledge about a protocol or an IP ? Or learning a new methodology or a new language? Finding corner case bugs? Thinking out of box ? – How can you become a great Verification Engineer ? Whether you are a young engineer entering VLSI Verification industry or aspiring to build a great career …
If you are a VLSI engineer in the current era of increasing IP (Intellectual Property) based SOC (System on Chip) designs, it is highly likely that you would have heard about AMBA, AHB, APB, AXI, AXI-lite, ACE etc somewhere or other. Given the large number of designs that use these you definitely would want to …
Understanding AMBA Bus Architecture and Protocols Read More »
