Another year of writing on Quora completed (2017) with more than 300+ answers. That fell short slightly below my goal of averaging an answer per day. Nevertheless it has been another wonderful experience.
I am happy to have helped those in need through these answers in the last year related to VLSI, Semiconductor and related topics.
Just like last year, here is a summary of the top 30 answers across 6 categories – in terms of most updates, views, shares and responses
Read on if you have missed any of those as you step in to another year of learning and be thankful.
What is the difference between soft IP and hard IP in VLSI?
What are the common sources of “x” in simulations for an SOC/ASIC design?
What is the scope of machine learning in verification?
How does a C test case and SV test bench interact, and what is the exact run flow in a SOC?
Which one is more efficient and faster in order to verify your design in VLSI, simulation or emulation? Which one is good? Is emulation going to be used more in the future?
SystemVerilog /UVM Related
What is a p_sequencer and an m_sequencer in UVM?
What is static casting and dynamic casting, and how can we differentiate them?
What is the best way to model an out-of-order transaction driver in UVM?
How do we end test case in SoC and SV-UVM?
Is it good to start learning UVM through the IEEE std 1800.2-2017 reference manual?
What is the largest semiconductor chip that has ever been built?
What is a Y chart in VLSI?
What interconnection will be used in future multi-core processor systems?
Will there be another mainstream architecture after x86 and ARM?
What is microarchitecture in VLSI design?
VLSI Career Related
What does the industry expect from VLSI verification engineers with different experience levels?
Is a VLSI job good for one’s career?
Is HDL coding a software job or a hardware job?
As a VLSI verification engineer, what are the things I should keep reading?
What are the different roles in verification in VLSI? How do they differ from each other?
Questions from Fresher/Entry Level Engineers
What are the challenges that a fresher will have to face after getting into the VLSI industry?
Is it true that VLSI digital design engineers are already in surplus in the industry?
Are jobs in the VLSI domain less relative to the number of graduates and number of post-graduates?
Is there any pressure in VLSI jobs?
Where/How can I find a mentor for a VLSI engineer?
Answers from My Experiences
How much time did you spend preparing for Intel’s interviews?
How hard is it for a test engineer (post silicon validation) to move on to VLSI field (front end or back end)?
What are the hard parts for a startup to make something to compete with the Intel x86?
What are all the contents should I added in resume as a verification engineer?
I’ve been an ASIC design engineer for the 15 years. I’d like to switch to a less stressful career with more growth outlook. What do you suggest?
Hope these helped you in some way or other.
Thank you and feel free to reach out with more questions and more learning in the new year 2018
Best wishes for a great new year 2018 !
PS: If you want to read a summary of previous year (2016) answers, you can find it here
My top answers of 2016 across VLSI, Semiconductor, Career, Interviews, Verification by Ramdas Mozhikunnath on Verification Excellence – Learn , Excel and Advance in Functional Verification
Also do follow blog on Verification Excellence – Learn , Excel and Advance in Functional Verification
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