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Implementing randc behavior using regular constraints in SystemVerilog

Blogs, SystemVerilog and UVM / By

In SystemVerilog, variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range.  For eg: consider  a 2 bit variable declared as     randc bit [1:0] y; Every time this variable is randomized,  the values are iterated over the possible range (in this case 0,1,2,3)  …

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How similar is an ASIC verification job compared to a Software coding profile?

FunctionalVerification, VLSI Career / By

An ASIC or SOC Verification job is increasingly becoming like a Software coding and debugging profile. However what is different is that you also need to be thinking like a hardware engineer while you apply some of the software engineering practices in coding and debug. Most of Verification infrastructure (test bench, stimulus generation, build, regression, …

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VLSI Product vs Service Companies

Product Companies vs Service Companies in VLSI

VLSI Career, VLSI Design / By

There are mainly two types of companies in the VLSI/Semiconductor industry. Quite often entry level engineers gets confused between these and wonder what are the differences and which one is better in terms of career.    Here are some details which hopefully will give you some insights. Product Companies : The companies designs and develops products …

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Verification Engineer Career Path

Verification Engineer Career- Opportunities and Path

Blogs, FunctionalVerification, VLSI Career, VLSI Design / By

Introduction One of the big job opportunities in VLSI Design spectrum is  front end verification engineer. The demand for verification engineers has been increasingly over last decade and is also getting more and more importance. Note: If you are new to VLSI Design life cycle, you might want to read  VLSI – Front end vs …

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What is a p_sequencer and an m_sequencer in UVM?

SystemVerilog and UVM / By

In SystemVerilog based OVM/UVM methodologies,  UVM sequences are objects with limited life time unlike a component which has a lifetime through out simulation. UVM Testbench – Sequences vs  Components Refer following standard UVM test bench diagram for a general concept.  All components like  test, env, scoreboard, agent, monitor, sequencer and driver  are derived from   uvm_component  …

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