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Opportunities For Electronics Engineering Graduates

This week, I got an invite to talk to a batch of final year Electronics Engineering Students who was undergoing a 4 week internship training as part of curriculum. The students have completed 6 semesters of their graduation program and completed course work on Semiconductors, Digital Electronics, Embedded Systems, Micro Controllers, Verilog, C programming and …

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Verification Validation Testing

Verification, Validation, Testing of ASIC and SOC designs – What are the differences?

Do you know differences between Verification, Validation and Testing of ASIC / SOC designs in the VLSI/chip design life cycles? If you are involved in any ASIC/SOC design life cycle, it is highly likely that you would have heard questions like – Have you verified a feature?  Is all feature testing completed?  How will you …

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My top answers of 2017 across VLSI, Semiconductor, Verification, Interviews and Career

Another year of writing on Quora completed (2017) with more than 300+ answers. That fell short slightly below my goal of averaging an answer per day. Nevertheless it has been another wonderful experience. I am happy to have helped those in need through these answers in the last year related to VLSI, Semiconductor and related …

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Cracking Digital VLSI Verification Interviews: Interview Success – A unique book

A large number of jobs in semiconductor industry fall in the category of Digital VLSI Design and Verification. With digital designs becoming more and more complex, demand of Digital VLSI Verification Engineers is on the rise. Increase in design complexity has not only led to an increase in the number of VLSI Verification jobs but …

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Verification Interview Questsions

What are your best ASIC Verification Interview Questions?

This question arises in every one’s mind while preparing for an ASIC Verification Interview. A lot of times in addition to understanding the technical concepts, you also needs to focus your preparation aligning with expectations from the interviewer and practice some of the commonly asked questions. This helps you to gain confidence and answer any related …

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Test your UVM skills for a VLSI front end Verification job

UVM (Universal Verification Methodology) is a SystemVerilog language based Verification methodology which is getting more and more popularity and adoption in the VLSI Verification industry. The methodology is currently in the IEEE working group 1800.2 and is expected to be an IEEE standard shortly.  What are some of UVM Interview questions that can test your …

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