chip design

Related to designing integrated circuit chips

Verification Validation Testing

Verification, Validation, Testing of ASIC and SOC designs – What are the differences?

Do you know differences between Verification, Validation and Testing of ASIC / SOC designs in the VLSI/chip design life cycles? If you are involved in any ASIC/SOC design life cycle, it is highly likely that you would have heard questions like – Have you verified a feature?  Is all feature testing completed?  How will you …

Verification, Validation, Testing of ASIC and SOC designs – What are the differences? Read More »

Test your UVM skills for a VLSI front end Verification job

UVM (Universal Verification Methodology) is a SystemVerilog language based Verification methodology which is getting more and more popularity and adoption in the VLSI Verification industry. The methodology is currently in the IEEE working group 1800.2 and is expected to be an IEEE standard shortly.  What are some of UVM Interview questions that can test your …

Test your UVM skills for a VLSI front end Verification job Read More »

error

Enjoy this blog? Please spread the word :)